Sliding synchronous/asynchronous trade-off curves
نویسندگان
چکیده
We discuss the options in developing a design flow for asynchronous circuits using a deep submicron technology based on standard commercial EDA tools. The flow starts with a synthesizable HDL specification, using the standard synchronous mechanisms, and produces a fabricatable layout GDSII form. It addresses the electro-magnetic interference, power, performance and timing-convergence issues by eliminating the clock network from a circuit. The trade-offs in terms of simplicity versus efficiency of the suggested flow are estimated through the exploration of the amount of “asynchrony” that an implementation exhibits.
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